CY7C1302CV25 Datasheet, PDF (12/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

TAP Controller State Diagram^[24]
PREMILINARY
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/ ¹
IDLE
SELECT
1
DR-SCAN
0
1
CAPTURE-DR
0
SHIFT-DR
0
1
1
EXIT1-DR
0
PAUSE-DR
0
1
0
EXIT2-DR
1
UPDATE-DR
1
0
Note:
24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C1302CV25
1
SELECT
IR-SCAN
0
1
CAPTURE-DR
0
SHIFT-IR
0
1
EXIT1-IR
1
0
PAUSE-IR
0
1
0
EXIT2-IR
1
UPDATE-IR
1
0
Document #: 38-05491 Rev. *A
Page 12 of 18