CY7C1302CV25 Datasheet, PDF (14/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

PREMILINARY
CY7C1302CV25
TAP AC Switching Characteristics Over the Operating Range (continued) ^{[26, 27]}
Parameter
Description
Output Times
t_TDOV
t_TDOX
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TAP Timing and Test Conditions^[27]
Min.
Max.
Unit
20
ns
0
ns
1.25V
TDO
Z₀ = 50Ω
50Ω
C_L = 20 pF
ALL INPUT PULSES
2.5V
1.25V
0V
(a) _GND
t_TH
t_TL
Test Clock
TCK
Test Mode Select
TMS
Test Data-In
TDI
t_TMSS
t_TDIS
t_TCYC
t_TMSH
t_TDIH
Test Data-Out
TDO
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Value
CY7C1302CV25
001
01011010010010110
00000110100
1
t_TDOX
t_TDOV
Description
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Document #: 38-05491 Rev. *A
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