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CY7C1302CV25 Datasheet, PDF (6/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
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PREMILINARY
CY7C1302CV25
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.5V
DC Input Voltage[9 .............................. –0.5V to VDDQ + 0.5V
Current into Outputs (LOW) .........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient
Range Temperature (TA)
Com’l
0°C to +70°C
VDD[10]
2.5 ± 0.1V
VDDQ[10]
1.4V to 1.9V
Electrical Characteristics Over the Operating Range[11]
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
VDD
VDDQ
VOH
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
IX
IOZ
VREF
IDD
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9, 14]
Clock Input Voltage
Input Load Current
Output Leakage Current
Input Reference Voltage[15]
VDD Operating Supply
2.4
1.4
Note 12
VDDQ/2 – 0.12
Note 13
VDDQ/2 – 0.12
IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2
IOL = 0.1 mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
–0.3
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical value = 0.75V
–5
–5
0.68
VDD = Max.,
IOUT = 0 mA,
f = fMAX = 1/tCYC
167 MHz
133 MHz
100 MHz
2.5
1.5
0.75
ISB1
Automatic
Power-Down
Current
Max. VDD, Both Ports 167 MHz
Deselected, VIN ≥ VIH or
VIN ≤ VIL, f =
fMAX = 1/tCYC,
133 MHz
100 MHz
Inputs Static
AC Input Requirements Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
VIH
Input High (Logic 1) Voltage
VREF + 0.2
VIL
Input Low (Logic 0) Voltage
–
Notes:
9. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2).
10. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
11. All voltage referenced to Ground.
12. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
13. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
14. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V.
15. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
Max.
2.6
1.9
VDDQ/2 + 0.12
VDDQ/2 + 0.12
VDDQ
0.2
VDDQ + 0.3
VREF –0.1
VDDQ+0.3
5
5
0.95
750
650
550
470
450
430
Max.
–
VREF – 0.2
Unit
V
V
V
V
V
V
V
V
V
µA
µA
V
mA
mA
mA
mA
mA
mA
Unit
V
V
Document #: 38-05491 Rev. *A
Page 6 of 18
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