CY7C1302CV25 Datasheet, PDF (7/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

PREMILINARY
CY7C1302CV25
Thermal Resistance^[16]
Parameter
Description
Θ_JA Thermal Resistance (Junction to Ambient)
Θ_JC Thermal Resistance (Junction to Case)
Test Conditions
165 FBGA Package Unit
Test conditions follow standard test
16.7
°C/W
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
2.5
°C/W
Capacitance^[16]
C_IN
C_CLK
C_O
Parameter
Description
Input Capacitance
Clock Input Capacitance
Output Capacitance
Test Conditions
T_A = 25°C, f = 1 MHz,
V_DD = 2.5V.
V_DDQ = 1.5V
Max. Unit
5
pF
6
pF
7
pF
AC Test Loads and Waveforms
V_REF
OUTPUT
Device
Under
Test
ZQ
(a)
V_DDQ/2
Z₀ = 50Ω
RQ =
250Ω
V_REF
R_L = 50Ω
V_REF = 0.75V
OUTPUT
Device
Under
Test _ZQ
INCLUDING
JIG AND
SCOPE
V_DDQ/2
V_DDQ/2
R = 50Ω
RQ =
250Ω
(b)
5 pF ^0.25V
[17]
ALL INPUT PULSES
1.25V
0.75V
Switching Characteristics Over the Operating Range ^[17]
Cypress
Parameter
t_Power[18]
Cycle Time
Consortium
Parameter
Description
V_CC (typical) to the First Access Read or Write
-167
-133
-100
Min. Max. Min. Max. Min. Max. Unit
10
10
10
µs
t_CYC
t_KH
t_KL
t_KHKH
t_KHKH
t_KHKL
t_KLKH
t_KHKH
K Clock and C Clock Cycle Time
6.0
7.5
10.0
ns
Input Clock (K/K and C/C) HIGH
2.4
3.2
3.5
ns
Input Clock (K/K and C/C) LOW
2.4
3.2
3.5
ns
K/K Clock Rise to K/K Clock Rise and C/C to C/C 2.7 3.3 3.4 4.1 4.4 5.4 ns
Rise (rising edge to rising edge)
t_KHCH
t_KHCH
K/K Clock Rise to C/C Clock Rise (rising edge to 0.0 2.0 0.0 2.5 0.0 3.0 ns
rising edge)
Set-up Times
t_SA
t_SA
Address Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
t_SC
t_SC
Control Set-up to Clock (K and K) Rise (RPS, 0.7
0.8
1.0
ns
WPS, BWS₀, BWS₁)
t_SD
t_SD
D_[17:0] Set-up to Clock (K and K) Rise
0.7
0.8
1.0
ns
Notes:
16. Tested initially and after any design or process change that may affect these parameters.
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, V_DDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified I_OL/I_OH and load capacitance shown in (a) of AC test loads.
18. This part has a voltage regulator that steps down the voltage internally; t_Power is the time power needs to be supplied above V_DD minimum initially before a read
or write operation can be initiated.
Document #: 38-05491 Rev. *A
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