CY7C1302CV25 Datasheet, PDF (15/18 Pages) Cypress Semiconductor – 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture

PREMILINARY
CY7C1302CV25
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
SAMPLE Z
010
RESERVED
011
SAMPLE/PRELOAD
100
RESERVED
101
RESERVED
110
BYPASS
111
Boundary Scan Order
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Bit Size
3
1
32
107
Description
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Bump ID
6R
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
Boundary Scan Order (continued)
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Bump ID
9J
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
10D
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
Document #: 38-05491 Rev. *A
Page 15 of 18