LUPA-1300_09 Datasheet, PDF (19/32 Pages) Cypress Semiconductor – 1.3MPxl High Speed CMOS Image Sensor

LUPA-1300
Standard timing (ROT = 200 ns
Figure 17. Only pre_col and Norowsel control signals are required. SH_col is made active low.)
In this case the control signals Norowsel and pre_col are made
active for about 50 nsec from the moment the next line is
selected. The time these pulses have to be active is related
with the biasing resistance Pre_load. The lower this resis-
tance, the shorter the pulse duration of Norowsel and pre_col
may be. After these pulses are given, one has to wait for 180
nsec before the first pixels can be sampled. For this mode
Sh_col must be made active low.
Timing of the Serial Parallel Interface (SPI)
The serial parallel interface is used to upload the x- and
y-address into the x- and y-address registers. This address is
the starting point of the window of interest and is uploaded in
the shift register by means of the corresponding synchroni-
zation pulse.
The elementary unit cell of the serial to parallel interface is
shown in Figure 18. 16 of these cells are connected in parallel,
having a common Load_addr and Clock_spi form the entire
uploadable address block. The uploaded addresses are
applied to the sensor on the rising edge of signal Load_addr.
Figure 18. Schematic of the SPI interface
To address registers
16 outputs to sensor : 6 x-address
bits and 10 y-address bits
Load_address
Address_in
Clock_spi
D
Q
C
D
Q
C
Address
Clock_spi
Load_addr
Address_out
Clock_spi
E ntire uploadable addres s block
Unity C ell
address
Load_addr
The SPI clock can have a frequency of 20 MHz and the data
is loaded into the register at the rising edge. The load_addr
A1
A2
A3
A16
command
applied to
sensor
pulse should go high together or after the last falling edge of
the SPI_clock (see Figure 18).
Document Number: 38-05711 Rev. *C
Page 19 of 32
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