LUPA-1300_09 Datasheet, PDF (15/32 Pages) Cypress Semiconductor – 1.3MPxl High Speed CMOS Image Sensor

LUPA-1300
Table 9 summarizes the relation between the internal and
external pixel array signals
Table 9. Overview of the internal and external pixel array signals.
Internal signal
Precharge
Sample
Reset
Vmemory
Vlow
0
0
0V
4.5V
Vhigh
5V
5V
4 - 6V
6V
External control
signal
Precharge
Sample
Reset & Reset_ds
Mem_hl
Low dc level
Gnd
Gnd
Gnd_res
Vmem_l
High dc level
Vddr
Vddr
Vres & Vres_ds
Vmem_h
The Precharge and Sample signals are the most straight-
forward signals. The internal signal Vmemory is a signal that
switches between a low voltage (3.5 - 5.5V) and a high voltage
(5-6V). The signal Mem_hl controls the applied level and the
power supply lines Vmem_l and Vmem_h determine the low
and high dc-levels.
The Reset signal is due to the dual slope technique a little
more complex. In case the dual slope is not used, the reset
signal is straightforward generated from the external reset
pulse. In this case the supply voltage Vres determines the
level to which the pixel is resetted.
In case the dual slope operation is desired, one needs to give
a second pulse to a lower reset level during integration. This
can be done by the control signal Reset_ds and by the power
supply Vres_ds that defines the level to which the pixel has to
be resetted.
If a pulse is given on the Reset_ds signal, a second pulse on
the internal reset line is generated to a lower level, determined
by the supply Vres_ds. If no Reset_ds pulse is given, the dual
slope technique is not implemented.
Note that Reset is dominant over Reset_ds, which means that
the high voltage level will be applied for reset, if both pulses
occur at the same time.
The external control signals should be capable of driving input
capacitance of about 20 pF.
Digital signals
The digital signals control the readout of the image sensor.
These signals are:
• Sync_y: Starts the readout of the frame or window at the
address defined by the y-address register. This pulse
synchronizes the y-address register: active high. This signal
is at the same time the end of the frame or window and
determines the window width.
• Clock_y: Clock of the y-register. On the rising edge of this
clock, the next line is selected.
• Sync_x: Starts the readout of the selected line at the
address defined by the x-address register. This pulse
synchronizes the x-address register: active high. This signal
is at the same time the end of the line and determines the
window length.
• Address: the x- and y-address is downloaded serial through
this signal.
• Clock_spi: clock of the serial parallel interface. This clock
downloads the address into the SPI register.
• Load_addr: when the SPI register is downloaded with the
desired address, the signal Load_addr signal loads the
x-and y-address into their address register as starting point
of the window of interest.
• Sh_col: control signal of the column readout. Is only used
in sample & hold mode (See timing)
• Norow_sel: Control signal of the column readout. Is only
used in Norow_sel mode (See timing)
• Pre_col: Control signal of the column readout to reduce row
blanking time
• Sel_active: activates the active load on chip for the output
amplifiers. If not used, a passive load can be used or one
can use this signal to put the output stages in standby mode
• Eos_x: end of scan signal: is an output signal, indicating
when the end of the line is reached. Is not generated when
doing windowing
• Eos_y: end of scan signal: is an output signal, indicating
when the end of the frame is reached. Is not generated when
doing windowing.
All digital signals are buffered and filtered on chip to remove
spikes and to achieve the required on chip driving speed. The
applied digital signals should be capable of driving 20 pF input
capacitance.
Test signals
Some test signals are required to evaluate the optical perfor-
mance of the image sensor. Other test signals allow us to test
internal modules in the image sensor and some test signals
will give us information concerning temperature and influence
of the temperature on the black level.
Evaluation on the optical performance (Spectral response, fill
factor)
• Array_diode
• Full_diode
Evaluation of the output stages:
• Black
• Dc_black
Evaluation of the x and y -shift registers:
• Eos_x
• Eos_y
Indication of the temperature and influence on the black level:
• Temp_diode_n
• Temp_diode_p
Document Number: 38-05711 Rev. *C
Page 15 of 32
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