LUPA-1300_09 Datasheet, PDF (14/32 Pages) Cypress Semiconductor – 1.3MPxl High Speed CMOS Image Sensor

LUPA-1300
Biasing and analog signals
Besides the biasing signals, the only analog signals are the
output signals Out1 - Out16. Each output signal is analog with
respect to the voltage level, but is discrete in time. This means
that on the speed of Clock_x, the outputs change to a different
level, depending on the illumination of the corresponding
pixels.
The biasing signals determine the speed and power dissi-
pation of the different modules on chip. These biasing signals
have to be connected trough a resistor to ground or power
supply and should be decoupled with a capacitor. If the sensor
is working properly, each of the biasing signals will have a
dc-voltage depending on the resistor value and on the internal
circuitry. These dc-voltages can be used to check the
operation of the image sensor. Table 8 gives the different
biasing signals, the way they should be connected, and the
expected dc-voltage. Due to small process variations, these
dc-voltages change from chip to chip and 10% variation is
possible.
Table 8. Overview of biasing signals
Signal
Comment
Expected dc-level
Pre_load
Connect with 10 KΩ to Vdda and capacitor of 100 nF to Gnd
2.0V
Col_load
Connect with 2 MΩ to Vdda and capacitor of 100 nF to Gnd
0.9V
Psf_load
Connect with 240 KΩ to Gnd and capacitor of 100 nF to Vdda
3.7V
Nsf_load
Connect with 100 KΩ to Vdda and capacitor of 100 nF to Gnd
1.3V
Load_out
Connect with 27 KΩ to Voo and capacitor of 100 nF to Gnd
1.6V
Decx_load
Connect with 27 KΩ to Gnd and capacitor of 100 nF to Vdd
2.8V
Decy_load
Connect with 27 KΩ to Gnd and capacitor of 100 nF to Vdd
2.8V
Each resistor controls the speed and power dissipation of the
corresponding module, as this resistor determines the current
required to charge and/or discharge internal nodes inside the
module.
A decoupling with a small capacitor is advisable to reduce the
HF noise onto the analog signals. Only the capacitor on the
Pre_load signal can be omitted.
Pixel array signals
Figure 4 in paragraph 2.2 is a schematic representation of the
pixel as used in the LUPA design. The applied signals to this
pixel are: reset, sample, Precharge, Vmemory, row select and
Vpix. These are internal generated signals derived by on chip
drivers from external applied signals. Consequently it is
important to understand the relation between both internal and
external signals and to understand the operation of the pixel.
The timing of the pixel is given in Figure 12 in which only the
internal signals are given.
Figure 12. Internal timing of the pixel.
At the end of the integration time, the information on the photo-
diode node needs to be sampled and stored onto the pixel
memory, required to allow synchronous shutter. To do this,
we need the signals "Precharge" and "Sample". "Precharge"
resets the pixel memory and "Sample" places the pixel infor-
mation onto the pixel memory. Once this information stored,
the readout of the pixel memories can start in parallel with a
new integration time. An additional signal "Vmem" is needed
to obtain a larger output swing.
Except from Vpix power supply, drivers generate the other
pixel signals on chip. The external signals to obtain the
required pulses consist of 2 groups. One is the group of digital
signals to indicate when the pulse must occur and the other
group is dc-supply lines indicating the levels of the pulses.
Document Number: 38-05711 Rev. *C
Page 14 of 32
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