STC4130 Datasheet, PDF (8/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

Addr
0x45
0x49
0x4d
Reg Name
T4_Short_Term_Accu_History
T4_User_Accu_History
T4_HO_BW_Ramp
0x4e
0x54
0x55
0x56
0x57
0x58
0x59
0x5a
0x5b
0x5c
0x5d
0x5e
0x60
T4_Priority_Table
T4_PLL_Status
T4_Accu_Flush
CLK0_Sel
CLK1_Sel
CLK2_Sel
CLK3_Sel
CLK4_Sel
CLK5_Sel
CLK6_Sel
CLK7_Sel
Intr_Event
Intr_Enable
STC4130
Synchronous Clock for SETS
Data Sheet
Table 4: Register Map
Bits
31-0
31-0
7-0
47-0
7-0
0-0
0-0
1-0
1-0
5-0
5-0
1-0
3-0
1-0
9-0
9-0
Type
R
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Short term Accumulated History for T4 relative to the TCXO
User Holdover data for T4 relative to the TCXO
Bits7-4, Long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2,
0.61, 0.03 mHz
Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62,
0.31 mHz
Bit21:0, Ramp control: none, 1, 1.5, 2 ppm/S
REF1-12 selection priority for automatic mode, 4 bits/reference
LTH Avail, LTH Complete, OOP, LOL, LOS, Sync
0: Flush current history, 1: Flush all histories
155.52 MHz clock enable/disable for CLK0
19.44MHz/38.88MHz/77.76MHz or disable select for CLK1
19.44MHz/38.88MHz/77.76MHz or disable select for CLK2
8KHz output 50% duty cycle or pulse width selection for CLK3
2KHz output 50% duty cycle or pulse width selection for CLK4
DS3/E3 select for CLK5
DS1 x n / E1 x n selector for CLK6
Ds1/E1 selector for CLK7
Interrupt event
Interrupt enable
Data Sheet #: TM084 Page 8 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice