STC4130 Datasheet, PDF (40/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

STC4130
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5f
Event 9:
Event 8:
Any refer- Any refer-
ence
ence
changed
changed
from dis- from quali-
qualified to fied to dis-
qualified
qualified
Interrupt event, 0 = no event, 1 = event occurred. Interrupt 8 and 9 apply to the 12 reference inputs only.
Interrupts are cleared by writing “1’s” to the bit positions to be cleared (See General Register Operation,
Clearing bits in the Interrupt Status Register section).
Intr_Enable, 0x60 (R/W)
Address
0x60
0x61
Bit7
Intr 7
Enable
Bit6
Intr 6
Enable
Bit5
Intr 5
Enable
Bit4
Intr 4
Enable
Interrupt disable/enable, 0 = disable, 1 = enable.
Default value: 0.
Bit3
Intr 3
Enable
Bit2
Intr 2
Enable
Bit1
Intr 1
Enable
Intr 9
Enable
Bit0
Intr 0
Enable
Intr 8
Enable
Application Notes
This section describes typical application use of the STC4130 device. The General section applies to all appli-
cation variations, while the remaining sections detail use depending on the level of control and automatic oper-
ation the application desires.
General
Power and Ground
Well-planned noise-minimizing power and ground are essential to achieving the best performance of the
device. The device requires 3.3 and 1.8V digital power and 1.8V analog power input. All digital I/O is at 3.3V,
LVTTL compatible. The 1.8V may originate from a common source but should be individually filtered and iso-
lated, as shown in Figure 17. Alternatively, a separate 1.8V regulator may be used for the analog 1.8 volts. R/C
filter components should be chosen for minimum inductance and kept as close to the chip as possible.
It is desirable to provide individual bypass capacitors, located close to the chip, for each of the digital power
input leads, subject to board space and layout constraints. On power-up, it is desirable to have the 1.8V either
lead or be coincident with, but not lag the application of 3.3V.
Digital ground should be provided by as continuous a ground plane as possible. While the analog and digital
grounds are tied together inside the chip, it is recommended that they be tied together externally at a single
point close to the chip as well.
Data Sheet #: TM084 Page 40 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice