STC4130 Datasheet, PDF (14/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

0x45-0x48).
On either transition, from Synchronized to Holdover,
or back from Holdover to Synchronized, an applica-
tion programmable maximum slew rate of 1, 1.5, or 2
ppm/second (or no slew rate limit) is applied, as writ-
ten to the T(0/4)_HO_Ramp registers (0x30/ 0x4d).
Output Clocks
The clock output section includes 4 clock genera-
tions, an APLL, and four dividers, and generates nine
synchronized clocks, as shown in figure 5.
T0 DPLL
Clk
Generation
APLL
Clk0
155.52 MHz
Clk1 _{19.44 / 38.88 /}
Divider
77.76 MHz
Divider
Clk2
19.44 / 38.88 /
77.76 MHz
Clk3
Divider
8 KHz
Clk4
Divider
2 KHz
Clk
Generation
Clk5
DS3, E3
Clk
Clk6 _{nxDS1, nxE1}
Generation
n = 1,2,4,8,16
T4 DPLL
Clk
Clk7
T1, E1
Generation
Figure 5: Output Clocks
The first synthesizer drives an analog PLL and gen-
erates five output clocks. It is driven from the T0
DPLL:
STC4130
Synchronous Clock for SETS
Data Sheet
ble pulse width, and may be disabled by writ-
ing to the CLK4_Sel register (0x5a), bits 0 -
5.
Two synthesizers generate additional clocks from the
T0 clock generator:
• CLK5: Either DS3 or E3 rate, or “disabled”,
programmed by writing to the CLK5_Sel reg-
ister (0x5b), bits 0 - 1.
• CLK6: Programmable at nxDS1 or nxE1
where n=1,2,4,8,16, or may be disabled, by
writing to the CLK6_Sel register (0x5c), bits
0 - 3.
One synthesizer is driven by the T4 clock generator:
• CLK7: Either DS1 or E1 rate, or “disabled”,
programmed by writing to the CLK7_Sel reg-
ister (0x5d), bits 0 - 1.
When a clock output is disabled, the pin is tri-stated.
In addition, the T0_Xsync_OUT and
T4_Xsync_OUT outputs provide phase information
and state data for master/slave operation of the T0
and T4 clock generators.
Note that the CLK1, 2, 5 and 6 are phase aligned
with the CLK3 (8KHz) as shown in Figure 7. CLk3 is
phase aligned with CLK4 (2KHz).
• CLK0: 155.52 MHz (LVPECL), enabled/dis-
abled by writing the CLK0_Sel register
(0x56), bit 0.
• CLK1: Programmable at 19.44MHz,
38.88MHz, 77.76 MHz, and “disabled”, by
writing to the CLK1_Sel register (0x57), bits
0 - 1.
• CLK2: Programmable at 19.44MHz,
38.88MHz, 77.76 MHz, and “disabled”, by
writing to the CLK2_Sel register (0x58), bits
0 - 1.
• CLK3: 8kHz, 50% duty cycle or programma-
ble pulse width, and may be disabled by writ-
ing to the CLK3_Sel register (0x59), bits 0 -
5.
• CLK4: 2kHz, 50% duty cycle or programma-
Data Sheet #: TM084 Page 14 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice