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STC4130 Datasheet, PDF (5/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS
Pin Name
BUS_AD6
BUS_AD5
BUS_AD4
BUS_AD3
BUS_AD2
BUS_AD1
BUS_AD0
BUS_INTR
REF1
REF2
REF3
REF4
REF5
REF6
REF7
REF8
REF9
REF10
REF11
REF12
T0_M/S
T4_M/S
T0_XSYNC_IN
T0_XSYNC_OUT
T4_XSYNC_IN
T4_XSYNC_OUT
CLK0_P
CLK0_N
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
Test_Pin
STC4130
Synchronous Clock for SETS
Data Sheet
Table 1: Pin Description
Pin #
42
40
39
37
36
34
33
32
2
4
5
8
10
12
14
16
17
19
21
23
24
28
25
70
26
66
85
86
83
81
79
77
74
72
68
7,11,96
I/O1
Description
I/O Parallel bus address/data bit6
I/O Parallel bus address/data bit5
I/O Parallel bus address/data bit4
I/O Parallel bus address/data bit3
I/O Parallel bus address/data bit2
I/O Parallel bus address/data bit1
I/O Parallel bus address/data bit0
O Interrupt
I Reference input 1
I Reference input 2
I Reference input 3
I Reference input 4
I Reference input 5
I Reference input 6
I Reference input 7
I Reference input 8
I Reference input 9
I Reference input 10
I Reference input 11
I Reference input 12
I Select master or slave mode for T0, 1: Master, 0: Slave
I Select master or slave mode for T4, 1: Master, 0: Slave
I
Cross-couple SyncLinkTM data link input fot T0 for master/slave redundant applications
O Cross-couple SyncLinkTM data link output fot T0 for master/slave redundant applications
I
Cross-couple SyncLinkTM data link input fot T4 for master/slave redundant applications
O Cross-couple SyncLinkTM data link output fot T4 for master/slave redundant applications
O 155.52 MHz LVDS output
O 155.52 MHz LVDS output
O 19.44/38.88/77.76 MHz
O 19.44/38.88/77.76 MHz
O 8 KHz frame pulse or 50% duty cycle clock
O 2 KHz frame pulse or 50% duty cycle clock
O 44.736/34.368 MHz
O 1.544/3.088/6.176/12.352/24.704/2.048/4.098/8.192/16.384/32.768 MHZ
O 1.544/2.048 MHz
I Test pin, must be grounded for normal operation
Data Sheet #: TM084 Page 5 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice