STC4130 Datasheet, PDF (24/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

STC4130
Synchronous Clock for SETS
Data Sheet
Multiplex Bus Mode
In multiplex bus mode, the device can interface with microprocessors which share the address and data on the
same bus signals. The BUS_ALE, BUS_CS, BUS_WRB, BUS_RDB, BUS_AD(7-0), and BUS_RDY pins are
used, corresponding to ALE, CS, WRB, RDB, AD, and RDY, respectively.
Multiplex Bus Timing
t_ALE
t_ALEd
ALE
t_ADs
t_ADh
t_CSs
CS
WRB
RDB
AD
Address
t_CSd
t_RDB
t_CSh
t_Dd1
t_Dh2
Data
RDY
t_RDYd1
t_RDYd2
t_RDY
t_RDYh
t_RDYd3
Figure 15: Multiplex Bus Read Timing
Table 10: Multiplex Bus Read Timing
Symbol
t_ALE
t_ALEd
t_ADs
t_ADh
t_CSs
t_RDB
t_CSh
t_CSd
t_Dd1
t_Dh2
t_RDYd1
t_RDYd2
t_RDY
t_RDYh
Description
ALE high time
ALE falling edge to RDB low
Address setup time
Address hold time
Read setup time
Read time
CS hold time
CS delay for multiple read/writes
Data valid delay from RDB low
Data high-z from RDB high
CS low to RDY active
RDB low to RDY low
RDY low time
Read hold after RDY high
Min
Max
Unit
10
nS
0
nS
10
nS
10
nS
0
nS
40
nS
0
nS
50
nS
50
nS
10
nS
13
nS
40
nS
50
nS
0
nS
Data Sheet #: TM084 Page 24 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice