STC4130 Datasheet, PDF (39/44 Pages) List of Unclassifed Manufacturers – Synchronous Clock for SETS

Default value: 2.
CLK6_Sel, 0x5c (R/W)
0x5b, bits 1 ~ 0
1
2
3
STC4130
Synchronous Clock for SETS
Data Sheet
CLK5 output
DS3
E3
Disabled
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5c
Not used
Selects or disables the CLK6 output. Default = 0110, 2.048MHz:
CLK6 Select
Default value: 1.
CLK7_Sel, 0x5d (R/W)
0x5c, bits 3 ~ 0
0
1
2
3
4
5
9
10
11
12
13
CLK6 output
Disabled
2.048MHz
4.096MHz
8.192MHz
16.384MHz
32.768MHz
1.544MHz
3.088MHz
6.176MHz
12.352Hz
24.704MHz
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5d
Selects or disables the CLK7 output.
Not used
CLK7 Select
Default value: 2.
Intr_Event, 0x5e (R/W)
0x5d, bits 1 ~ 0
0
1
2
3
CLK7 output
Disabled
T1
E1
Disabled
Address
0x5e
Bit7
Event 7:
T4 cross
reference
changed
from non-
active to
active
Bit6
Event 6:
T4 cross
reference
changed
from active
to non-
active
Bit5
Event 5:
T4 DPLL
status
changed
Bit4
Event 4:
T4 active
reference
changed in
auto selec-
tion mode
Bit3
Event 3:
T0 cross
reference
changed
from non-
active to
active
Bit2
Event 2:
T0 cross
reference
changed
from active
to non-
active
Bit1
Event 1:
T0 DPLL
status
changed
Bit0
Event 0:
T0 active
reference
changed in
auto selec-
tion mode
Data Sheet #: TM084 Page 39 of 44 Rev: P02 Date: 12/5/06
© Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice