EP9315 Datasheet, PDF (9/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
Universal Asynchronous
Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two
provide asynchronous HDLC (High-level Data Link
Control) protocol support for full-duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must assemble the frame in memory before
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. A third IrDA^®-
compatible UART is also supplied.
• UART1 supports modem bit rates up to 115.2 Kbps,
supports HDLC and includes a 16-byte FIFO for
receive and a 16-byte FIFO for transmit. Interrupts are
generated on Rx, Tx, and modem status change.
• UART2 contains an IrDA encoder operating at either
the slow (up to 115 Kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16-
byte FIFO for receive and a 16-byte FIFO for transmit.
• UART3 supports HDLC and includes a 16-byte FIFO
for receive and a 16-byte FIFO for transmit. Interrupts
are generated on Rx and Tx.
Triple Port USB Host
The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tiered-
start” topology.
This includes the following features:
• Compliance with the USB 2.0 specification
• Compliance with the Open HCI Rev 1.0 specification
• Supports both low speed (1.5 Mbps) and full speed
(12 Mbps) USB device connections
• Root HUB integrated with 3 downstream USB ports
• Transceiver buffers integrated, over-current protection
on ports
• Supports power management
• Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
• Fetches endpoint descriptors and transfer descriptors
• Accesses endpoint data from system memory
• Accesses the HC communication area
• Writes status and retire transfer descriptor
Table I. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
Pin Name - Description
TXD0
RXD0
CTSn
DSRn / DCDn
DTRn
RTSn
EGPIO[0] / RI
TXD1 / SIROUT
RXD1 / SIRIN
TXD2
RXD2
EGPIO[3] / TENn
UART1 Transmit
UART1 Receive
UART1 Clear To Send /
Transmit Enable
UART1 Data Set Ready /
Data Carrier Detect
UART1 Data Terminal Ready
UART1 Ready To Send
UART1 Ring Indicator
UART2 Transmit /
IrDA Output
UART2 Receive / IrDA Input
UART3 Transmit
UART3 Receive
HDLC3 Transmit Enable
Table J. Triple Port USB Host Pin Assignments
Pin Mnemonic
Pin Name - Description
USBp[2:0]
USBm[2:0]
USB Positive signals
USB Negative Signals
Two-wire Interface
The two-wire interface provides communication and
control for synchronous-serial-driven devices.
Table K. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic Pin Name - Description
Alternative
Usage
EECLK
EEDATA
Two-Wire Interface Clock
Two-Wire Interface Data
General
Purpose I/O
General
Purpose I/O
DS638PP4
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