EP9315 Datasheet, PDF (36/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
Ultra DMA Data Transfer
Figure 21 through Figure 30 define the timings associated with all phases of Ultra DMA bursts. The following table
contains the values for the timings for each of the Ultra DMA modes.
Timing reference levels = 1.5 V
Parameter
Symbol
Cycle time allowing for asymmetry and clock variations
(from DSTROBE edge to DSTROBE edge)
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of DSTROBE)
Cycle time allowing for asymmetry and clock variations
(from HSTROBE edge to HSTROBE edge)
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of HSTROBE)
Data setup time at recipient (Read)
Data hold time at recipient (Read)
Data valid setup time at sender (Write)
(from data valid until STROBE edge)
Data valid hold time at sender (Write)
(from STROBE edge until data may become invalid)
(Note 2)
(Note 2)
First STROBE time (for device to first negate DSTROBE from STOP
during a data in burst)
Limited interlock time
(Note 3)
Interlock time with minimum
(Note 3)
Unlimited interlock time
(Note 3)
Maximum time allowed for output drivers to release
(from asserted or negated)
Minimum delay time required for output
Drivers to assert or negate (from released)
Envelope time (from DMACKn to STOP and HDMARDYn during data in
burst initiation and from DMACKn to STOP during data out burst initiation)
Ready-to-final-STROBE time (no STROBE edges shall be sent this long
after negation of DMARDYn)
Ready-to-pause time
(that recipient shall wait to pause after negating DMARDYn)
Maximum time before releasing IORDY
Minimum time before driving STROBE
(Note 4)
Setup and hold times for DMACKn (before assertion or negation)
Time from STROBE edge to negation of DMARQ or assertion of STOP
(when sender terminates a burst)
t_CYCRD
t_2CYCRD
t_CYCWR
t_2CYCWR
t_DS
t_DH
t_DVS
t_DVH
t_FS
t_LI
t_MLI
t_UI
t_AZ
t_ZAH
t_ZAD
t_ENV
t_RFS
t_RP
t_IORDYZ
t_ZIORDY
t_ACK
t_SS
Mode 0
(in ns)
min max
112 -
230 -
230 -
460 -
15
-
8
-
70
-
6
-
0 230
0 150
20
-
0
-
-
10
20
-
0
-
20 70
-
75
160 -
-
20
0
-
20
-
50
-
Mode 1
(in ns)
min max
73
-
154 -
170 -
340 -
10
-
8
-
48
-
6
-
0 200
0 150
20
-
0
-
-
10
20
-
0
-
20 70
-
70
125 -
-
20
0
-
20
-
50
-
Mode 2
(in ns)
min max
54
-
115 -
130 -
260 -
7
-
8
-
30
-
6
-
0 170
0 150
20
-
0
-
-
10
20
-
0
-
20 70
-
60
100 -
-
20
0
-
20
-
50
-
Mode 3
(in ns)
min max
39
-
86
-
100 -
200 -
7
-
8
-
20
-
6
-
0 130
0 100
20
-
0
-
-
10
20
-
0
-
20 55
-
60
100 -
-
20
0
-
20
-
50
-
Note:
1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies.
2. The test load for t_DVS and t_DVH shall be a lumped capacitor load with no cable or receivers. Timing for t_DVS and t_DVH shall be
met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
3. t_UI, t_MLI and t_LI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the
other to respond with a signal before proceeding. t_UI is an unlimited interlock that has no maximum time value. t_MLI is a limited
time-out that has a defined minimum. t_LI is a limited time-out that has a defined maximum.
4. t_ZIORDY may be greater than t_ENV since the device has a pull up on IORDYn giving it a known state when released.
5. All IDE timing is based upon HCLK = 100 MHz.
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