EP9315 Datasheet, PDF (60/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
The following section focuses on the EP9315 pin signals
from two viewpoints - the pin usage and pad
characteristics, and the pin multiplexing usage. The first
table (Table S) is a summary of all the EP9315 pin
signals. The second table (Table T) illustrates the pin
signal multiplexing and configuration options.
Table S is a summary of the EP9315 pin signals, which
illustrates the pad type and pad pull type (if any). The
symbols used in the table are defined as follows. (Note: A
blank box means Not Applicable (NA) or, for Pull Type,
No Pull (NP).)
Under the Pad Type column:
• A - Analog pad
• P - Power pad
• G - Ground pad
• I - Pin is an input only
• I/O - Pin is input/output
• 4mA - Pin is a 4 mA output driver
• 8mA - Pin is an 8 mA output driver
• 12mA - Pin is an 12 mA output driver
See the text description for additional information about
bi-directional pins.
Under the Pull Type Column:
• PU - Resistor is a pull up to the RVDD supply
• PD - Resistor is a pull down to the RGND supply
.
Table S. Pin Descriptions
Pin Name
TCK
TDI
TDO
TMS
TRSTn
BOOT[1:0]
XTALI
XTALO
VDD_PLL
GND_PLL
RTCXTALI
RTCXTALO
WRn
RDn
WAITn
AD[25:0]
DA[31:0]
CSn[3:0]
CSn[7:6]
DQMn[3:0]
SDCLK
SDCLKEN
SDCSn[3:0]
RASn
CASn
SDWEn
P[17:0]
Block
JTAG
JTAG
JTAG
JTAG
JTAG
System
PLL
PLL
PLL
PLL
RTC
RTC
EBUS
EBUS
EBUS
EBUS
EBUS
EBUS
EBUS
EBUS
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
Raster
Pad Pull
Type Type
Description
I
PD JTAG clock in
I
PD JTAG data in
4ma
JTAG data out
I
PD JTAG test mode select
I
PD JTAG reset
I
PD Boot mode select in
A
Main oscillator input
A
Main oscillator output
P
Main oscillator power, 1.8V
G
Main oscillator ground
A
RTC oscillator input
A
RTC oscillator output
4ma
SRAM Write strobe out
4ma
SRAM Read / OE strobe out
I
PU SRAM Wait in
8ma
Shared Address bus out
8ma PU Shared Data bus in/out
4ma PU Chip select out
4ma PU Chip select out
8ma
Shared data mask out
8ma
SDRAM clock out
8ma
SDRAM clock enable out
4ma
SDRAM chip selects out
8ma
SDRAM RAS out
8ma
SDRAM CAS out
8ma
SDRAM write enable out
4ma PU Pixel data bus out
Table S. Pin Descriptions (Continued)
Pin Name
SPCLK
HSYNC
V_CSYNC
BLANK
BRIGHT
PWMOUT
Xp, Xm
Yp, Ym
sXp, sXm
sYp, sYm
VDD_ADC
GND_ADC
COL[7:0]
ROW[7:0]
USBp[2:0]
USBm[2:0]
TXD0
RXD0
CTSn
DSRn
DTRn
RTSn
TXD1
RXD1
TXD2
RXD2
MDC
Block
Raster
Raster
Raster
Raster
Raster
PWM
ADC
ADC
ADC
ADC
ADC
ADC
Key
Key
USB
USB
UART1
UART1
UART1
UART1
UART1
UART1
UART2
UART2
UART3
UART3
EMAC
Pad Pull
Type Type
Description
12ma
8ma
8ma
8ma
4ma
8ma
A
A
A
A
P
G
8ma
8ma
A
A
4ma
I
I
I
4ma
4ma
4ma
I
4ma
I
4ma
PU Pixel clock in/out
PU Horizontal synchronization / line pulse out
PU
Vertical or composite synchronization / frame
pulse out
PU Composite blanking signal out
PWM brightness control out
Pulse width modulator output
Touchscreen ADC X axis
Touchscreen ADC Y axis
Touchscreen ADC X axis feedback
Touchscreen ADC Y axis feedback
Touchscreen ADC power, 3.3V
Touchscreen ADC ground
PU Key matrix column inputs
PU Key matrix row outputs
USB positive signals
USB negative signals
Transmit out
PU Receive in
PU Clear to send / transmit enable
PU Data set ready / Data Carrier Detect
Data Terminal Ready output
Ready to send
Transmit / IrDA output
PU Receive / IrDA input
Transmit
PU Receive
Management data clock
60
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