EP9315 Datasheet, PDF (19/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

Static Memory Single Word Read Cycle
Parameter
AD setup to CSn assert time
AD hold from CSn deassert time
RDn assert time
CSn to RDn delay time
CSn assert to DQMn assert delay time
DA setup to RDn deassert time
DA hold from RDn deassert time
Symbol
t_ADs
t_ADh
t_RDpw
t_RDd
t_DQMd
t_DAs
t_DAh
See “Timing Conditions” on page 14 for definition of HCLK.
Min
0
t_HCLK
-
-
-
t_HCLK + 12
0
EP9315
Enhanced Universal Platform SOC Processor
Typ
-
-
t_HCLK × (WST1 + 2)
-
-
-
-
Max
-
-
-
3
1
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
AD
CSn
WRn
RDn
DQMn
DA
WAIT
t_ADs
t_ADh
t_RDd
t_DQMd
t_RDd
t_DAs
t_DAh
Figure 6. Static Memory Single Word Read Cycle Timing Measurement
DS638PP4
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