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| EP9315 Datasheet, PDF (42/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor | |||
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EP9315
Enhanced Universal Platform SOC Processor
HSTROBE
(host)
DD (15:0)
(host)
HSTROBE
(device)
DD (15:0)
(device)
tDVH
tDH
tCYCWR
t2CYCWR
tCYCWR
tDVS
tDVH
tDVS
t2CYCWR
tDVH
tDS
tDH
tDS
tDH
Note:
DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as
cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are
driven by the host.
Figure 27. Sustained Ultra DMA data-out Burst
DMARQ
(device)
DMACKn
(host)
STOP
(host)
DDMARDYn
(device)
HSTROBE
(host)
DD (15:0)
(host)
tRP
tSR
tRFS
Note:
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDYn is
negated.
2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 28. Device Pausing an Ultra DMA data-out Burst
42
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
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