EP9315 Datasheet, PDF (28/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
Static Memory Single Write Wait Cycle
Parameter
WAIT to WRn deassert delay time
CSn assert to WAIT time
WAIT assert time
WAIT to CSn deassert delay time
Symbol
t_WRd
t_WAITd
t_WAITpw
t_CSnd
Min
t_HCLK × 2
-
t_HCLK × 2
t_HCLK × 3
Typ
-
-
-
-
Max
t_HCLK × 4
t_HCLK × (WST1-2)
t_HCLK × 510
t_HCLK × 5
Unit
ns
ns
ns
ns
AD
CSn
WRn
RDn
DQMn
DA
WAIT
t_WRd
t_WAITd
t_WAITpw
t_CSnd
Figure 15. Static Memory Single Write Wait Cycle Timing Measurement
28
©Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4