EP9315 Datasheet, PDF (56/64 Pages) Cirrus Logic – Enhanced Universal Platform System-on-Chip Processor

EP9315
Enhanced Universal Platform SOC Processor
Symbol
A
A1
A2
b
c
D
D1
D2
D3
E
E1
E2
E3
e
ddd
q
Table R. 352 Pin Diagram Dimensions
dimension in mm
dimension in inches
MIN
NOM
MAX
MIN
NOM
MAX
2.20
-
1.12
-
0.51
26.80
-
23.80
17.95
26.80
-
23.80
17.95
-
-
2.30
0.60
1.17
0.75
0.56
27.00
24.13
24.00
18.00
27.00
24.13
24.00
18.00
1.27
-
30° TYP
2.50
-
1.22
-
0.61
27.20
-
24.20
18.05
27.20
-
24.20
18.05
-
0.15
0.087
-
0.044
-
0.020
1.055
-
0.937
0.707
1.055
-
0.937
0.707
-
-
0.092
0.024
0.046
0.030
0.022
1.063
0.950
0.945
0.709
1.063
0.950
0.945
0.709
0.050
-
30° TYP
0.098
-
0.048
-
0.024
1.071
-
0.953
0.711
1.071
-
0.953
0.711
-
0.006
Note:
1. Controlling Dimension: Millimeter.
2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls.
3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C.
4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge.
5. Reference Document: JEDEC MO-151, BAL-2
352 Pin BGA Pinout (Bottom View)
The following table shows the 352 pin BGA pinout. (For better understanding, compare the coordinates on the x and y
axis on Figure 40, "352 PIN BGA PINOUT", on page 57 with Figure 40, "352 Pin PBGA Pin Diagram", on page 55.
• VDD_core is CVDD.
• VDD_ring is RVDD.
• All core and ring grounds are connected together and are labelled GND.
• Other special power requirements are clearly labelled (i.e. H18=ADC_VDD and H19=ADC_GND).
• NC means that the pin is not connected.
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DS638PP4