CS2000-CP_15 Datasheet, PDF (8/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T_A = -10°C to +70°C (Commercial Grade);
T_A = -40°C to +85°C (Automotive-D Grade); T_A = -40°C to +105°C (Automotive-E Grade); C_L = 15 pF.
Parameters
Symbol
Conditions
Min Typ
Crystal Frequency
Fundamental Mode XTAL
f_XTAL
RefClkDiv[1:0] = 10
8
-
RefClkDiv[1:0] = 01 ¹⁶
-
RefClkDiv[1:0] = 00
32
-
Reference Clock Input Frequency
f_{REF_CLK} RefClkDiv[1:0] = 10
8
-
RefClkDiv[1:0] = 01 16
-
RefClkDiv[1:0] = 00 32
-
Reference Clock Input Duty Cycle
Internal System Clock Frequency
Clock Input Frequency
Clock Input Pulse Width (Note 4)
Clock Skipping Timeout
Clock Skipping Input Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
D_{REF_CLK}
45
-
f_{SYS_CLK}
8
f_{CLK_IN}
50 Hz
-
pw_{CLK_IN}
f_{CLK_IN} < f_{SYS_CLK}/96
2
-
f_{CLK_IN} > f_{SYS_CLK}/96
10
-
t_CS
(Notes 5, 6)
20
-
f_{CLK_SKIP}
(Note 6)
50 Hz
-
f_{CLK_OUT}
(Note 7)
6
-
t_OD
Measured at VD/2
45
50
t_OR
20% to 80% of VD
-
1.7
t_OF
80% to 20% of VD
-
1.7
t_JIT
(Note 8)
-
70
(Notes 8, 9)
-
50
Wide Band JItter (100 Hz Corner)
(Notes 8, 10)
-
175
PLL Lock Time - CLK_IN (Note 11)
t_LC
f_{CLK_IN} < 200 kHz
-
100
f_{CLK_IN} > 200 kHz
-
1
PLL Lock Time - REF_CLK
t_LR
f_{REF_CLK} = 8 to 75 MHz
-
1
Output Frequency Synthesis Resolution (Note 12)
f_err
High Resolution
0
-
High Multiplication
0
-
Max
14
28
50
14
28
56
55
14
30
-
-
-
80
75
55
3.0
3.0
-
-
-
200
3
3
±0.5
±112
Units
MHz
MHz
MHz
MHz
MHz
MHz
%
MHz
MHz
UI
ns
ms
kHz
MHz
%
ns
ns
ps rms
ps rms
ps rms
UI
ms
ms
ppm
ppm
Notes: 4.
5.
6.
1 UI (unit interval) corresponds to t_{SYS_CLK} or 1/f_{SYS_CLK}.
t_CS represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t_CS.
Only valid in clock skipping mode; See “CLK_IN Skipping Mode” on page 15 for more information.
7. f_{CLK_OUT} is ratio-limited when f_{CLK_IN} is below 72 Hz.
8. f_{CLK_OUT} = 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
9. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
10. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
11. 1 UI (unit interval) corresponds to t_{CLK_IN} or 1/f_{CLK_IN}.
12. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
8
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