CS2000-CP_15 Datasheet, PDF (31/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.5.2
CS2000-CP
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
EnDevCfg2
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 25
Note: EnDevCfg1 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 25.
8.6 Ratio 0 - 3 (Address 06h - 15h)
7
MSB
MSB-8
LSB+15
LSB+7
6
5
4
3
2
1
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0
MSB-7
MSB-15
LSB+8
LSB
These registers contain the User Defined Ratios as shown in the “Register Quick Reference” section on
page 27. Each group of 4 registers forms a single 32-bit ratio value as shown above. See “Output to Input
Frequency Ratio Configuration” on page 19 and “Calculating the User Defined Ratio” on page 34 for more
details.
8.7 Function Configuration 1 (Address 16h)
7
ClkSkipEn
6
AuxLockCfg
5
Reserved
4
RefClkDiv1
3
RefClkDiv0
2
Reserved
1
Reserved
0
Reserved
8.7.1
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
ClkSkipEn
0
1
Application:
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 15
Note: f_{CLK_IN} must be < 80 kHz and re-applied within 20 ms to use this feature.
DS761F3
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