CS2000-CP_15 Datasheet, PDF (11/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-CP
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; C_L = 20 pF.
Parameter
Symbol
Min
Max
CCLK Clock Frequency
f_ccllk
-
6
CCLK Edge to CS Falling
(Note 14)
t_spi
500
-
CS High Time Between Transmissions
t_csh
1.0
-
CS Falling to CCLK Edge
t_css
20
-
CCLK Low Time
t_scl
66
-
CCLK High Time
t_sch
66
-
CDIN to CCLK Rising Setup Time
t_dsu
40
-
CCLK Rising to DATA Hold Time
(Note 15)
t_dh
15
-
Rise Time of CCLK and CDIN
(Note 16)
t_r2
-
100
Fall Time of CCLK and CDIN
(Note 16)
t_f2
-
100
Delay from Supply Voltage Stable to Control Port Ready
t_dpor
100
-
Unit
MHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
µs
Notes: 14. t_spi is only needed before first falling edge of CS after power is applied. t_spi = 0 at all other times.
15. Data must be held for sufficient time to bridge the transition time of CCLK.
16. For f_cclk < 1 MHz.
VD
t_dpor
CS
CCLK
CDIN
t _spi t_css
t _scl t _sch
t_csh
t _r2
t _f2
t _{dsu tdh}
Figure 6. Control Port Timing - SPI Format (Write Only)
DS761F3
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