CS2000-CP_15 Datasheet, PDF (19/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

5.3 Output to Input Frequency Ratio Configuration
CS2000-CP
5.3.1
User Defined Ratio (R_UD), Frequency Synthesizer Mode
The User Defined Ratio, R_UD, is a 32-bit un-signed fixed-point number which determines the basis for the
desired input to output clock ratio. Up to four different ratios, Ratio_0-3, can be stored in the CS2000 register
space. The ratio pointed to by the RSel[1:0] bits is the currently selected ratio for the static ratio based
Frequency Synthesizer Mode. The 32-bit R_UD is represented in a high-resolution 12.20 format where the
12 MSBs represent the integer binary portion while the remaining 20 LSBs represent the fractional binary
portion. The maximum multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this
configuration. See “Calculating the User Defined Ratio” on page 34 for more information.
The status of internal dividers, such as the internal timing reference clock divider, are automatically taken
into account. Therefore R_UD is simply the desired ratio of the output to input clock frequencies.
Referenced Control
Register Location
Ratio_0-3.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 31
Rsel[1:0] ................................“Ratio Selection (RSel[1:0])” on page 29
5.3.2
User Defined Ratio (R_UD), Hybrid PLL Mode
The same four ratio locations, Ratio_0-3, are used to store the User Defined Ratios for Hybrid PLL Mode.
The User Defined Ratio pointed to by the LockClk[1:0] bits is the currently selected ratio for the dynamic
ratio based Hybrid PLL Mode.
In addition to the High-Resolution format, a High-Multiplication format is also available. In the High-Multi-
plication Format Mode, the 32-bit R_UD is represented in a 20.12 format where the 20 MSBs represent the
integer binary portion while the remaining 12 LSBs represent the fractional binary portion. In this config-
uration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 PPM.
The ratio format default is 20.12. The 20.12 ratio format is only available when both the LFRatioCfg bit is
cleared (20.12) and the FracNSrc bit is set (dynamic ratio). In Auto Fractional-N Source Mode (see section
5.3.5.2 on page 21) when CLK_IN is not present the LFRatioCfg bit is ignored and the ratio format is
12.20.
It is recommended that the 12.20 High-Resolution format be utilized whenever the desired ratio is less
than 4096 since the output frequency accuracy of the PLL is directly proportional to the accuracy of the
timing reference clock and the resolution of the R_UD.
Referenced Control
Register Location
LockClk[1:0] ..........................“Lock Clock Ratio (LockClk[1:0])” section on page 30
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 32
FracNSrc ...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
DS761F3
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