CS2000-CP_15 Datasheet, PDF (33/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.9 Function Configuration 3 (Address 1Eh)
7
Reserved
6
ClkIn_BW2
5
ClkIn_BW1
4
ClkIn_BW0
3
Reserved
2
Reserved
CS2000-CP
1
Reserved
0
Reserved
8.9.1
Clock Input Bandwidth (ClkIn_BW[2:0])
Sets the minimum loop bandwidth when locked to CLK_IN.
ClkIn_BW[2:0]
000
001
010
011
100
101
110
111
Application:
Minimum Loop Bandwidth
1 Hz
2 Hz
4 Hz
8 Hz
16 Hz
32 Hz
64 Hz
128 Hz
“Adjusting the Minimum Loop Bandwidth for CLK_IN” on page 17
Note: In order to guarantee that a change in minimum bandwidth takes effect, these bits must be set
prior to acquiring lock (removing and re-applying CLK_IN can provide the unlock condition necessary to
initiate the setting change). In production systems these bits should be configured with the desired values
prior to setting the EnDevCfg bits; this guarantees that the setting takes effect prior to acquiring lock.
DS761F3
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