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CS2000-CP_15 Datasheet, PDF (1/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier | |||
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CS2000-CP
Fractional-N Clock Synthesizer & Clock Multiplier
Features
ï´ Delta-Sigma Fractional-N Frequency Synthesis
â Generates a Low Jitter 6 - 75 MHz Clock
from an 8 - 75 MHz Reference Clock
ï´ Clock Multiplier / Jitter Reduction
â Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to
30 MHz Clock Source
ï´ Highly Accurate PLL Multiplication Factor
â Maximum Error Less Than 1 PPM in High-
Resolution Mode
ï´ I²C / SPI⢠Control Port
ï´ Configurable Auxiliary Output
ï´ Flexible Sourcing of Reference Clock
â External Oscillator or Clock Source
â Supports Inexpensive Local Crystal
ï´ Minimal Board Space Required
â No External Analog Loop-filter
Components
The CS2000-CP is an extremely versatile system
clocking device that utilizes a programmable phase
lock loop. The CS2000-CP is based on a hybrid ana-
log-digital PLL architecture comprised of a unique
combination of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for both frequency synthesis/clock generation from a
stable reference clock as well as generation of a low-
jitter clock relative to an external noisy synchronization
clock. The design is also unique in that it can generate
low-jitter clocks relative to noisy external synchroniza-
tion clocks at frequencies as low as 50 Hz. The
CS2000-CP supports both I²C and SPI for full software
control.
The CS2000-CP is available in a 10-pin MSOP
package in Commercial (-10°C to +70°C), Automotive-
D (-40°C to +85°C), and Automotive-E (-40°C to
+105°C) grades. Customer development kits are also
available for device evaluation. Please see âOrdering
Informationâ on page 36 for complete details.
I²C/SPI
Software Control
I²C / SPI
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
Auxiliary
Output
8 MHz to 75 MHz
Low-Jitter Timing
Reference
50 Hz to 30 MHz
Frequency
Reference
http://www.cirrus.com
Fractional-N
Frequency Synthesizer
Output to Input
N
Clock Ratio
Digital PLL & Fractional
N Logic
Output to Input
Clock Ratio
Copyright ï£ Cirrus Logic, Inc. 2009â2015
(All Rights Reserved)
6 to 75 MHz
PLL Output
SEPT '15
DS761F3
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