CS2000-CP_15 Datasheet, PDF (16/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-CP
output will resume.
CLK_IN
2²³ SysClk cycles
Lock Time
CLK_IN
2²³ SysClk cycles
Lock Time
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
= invalid clocks
Figure 13. CLK_IN removed for > 2²³ SysClk cycles
If it is expected that CLK_IN will be removed and then reapplied within 2²³ SysClk cycles but later than
t_CS, the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in
Figure 14; note that the lower figure shows that the PLL output frequency may change and be incorrect
without an indication of an unlock condition.
tCS
2²³ SysClk cycles
Lock Time
tCS
2²³ SysClk cycles
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
= invalid clocks
CLK_IN
tCS
2²³ SysClk cycles
Lock Time
ClkSkipEn= 1
ClkOutUnl= 0 or 1
PLL_OUT
UNLOCK
= invalid clocks
Figure 14. CLK_IN removed for < 2²³ SysClk cycles but > t_CS
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