CS2000-CP_15 Datasheet, PDF (32/37 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.7.2
CS2000-CP
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If AUX-
_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg
0
1
Application:
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 23
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.7.3
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
RefClkDiv[1:0]
00
01
10
11
Application:
Reference Clock Input Divider
REF_CLK Frequency Range
÷ 4.
32 MHz to 56 MHz (50 MHz with XTI)
÷ 2.
16 MHz to 28 MHz
÷ 1.
8 MHz to 14 MHz
Reserved.
“Internal Timing Reference Clock Divider” on page 14
8.8 Function Configuration 2 (Address 17h)
7
Reserved
6
Reserved
5
Reserved
4
ClkOutUnl
3
LFRatioCfg
2
Reserved
1
Reserved
0
Reserved
8.8.1
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl
0
1
Application:
Clock Output Enable Status
Clock outputs are driven ‘low’ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 23
8.8.2
Low-Frequency Ratio Configuration (LFRatioCfg)
Determines how to interpret the currently indexed 32-bit User Defined Ratio when the dynamic ratio based
Hybrid PLL Mode is selected (either manually or automatically, see section 5.3.5 on page 21).
LFRatioCfg
0
1
Application:
Ratio Bit Encoding Interpretation when Input Clock Source is CLK_IN
20.12 - High Multiplier.
12.20 - High Accuracy.
“User Defined Ratio (RUD), Hybrid PLL Mode” on page 19
Note: When the static ratio based Frequency Synthesizer Mode is selected (either manually or auto-
matically), the currently indexed User Defined Ratio will always be interpreted as a 12.20 fixed point value,
regardless of the state of this bit.
32
DS761F3