CS42L51_07 Datasheet, PDF (46/88 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
5. REGISTER QUICK REFERENCE
Software mode register defaults are as shown. “Reserved” registers must maintain their default state.
Addr Function
7
6
5
4
3
2
1
0
01h ID
p 49
default
02h Power Ctl. 1
Chip_ID4
1
Chip_ID3
1
Chip_ID2
0
Chip_ID1
1
Chip_ID0
1
Rev_ID2
0
Rev_ID1
0
Rev_ID0
1
Reserved PDN_DACB PDN_DACA dPDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA
PDN
p 49
default
0
0
0
0
0
03h Speed Ctl. &
Power Ctl. 2
AUTO
SPEED1 SPEED0
3-ST_SP PDN_MICB
p 50
default
1
0
1
0
1
04h Interface Ctl. SDOUT->SDIN M/S
DAC_DIF2 DAC_DIF1 DAC_DIF0
p 52
default
0
0
0
0
0
05h MIC Control ADC_SNGVOL ADCB_
& Misc.
DBOOST
ADCA_
DBOOST
MICBIAS_ MICBIAS_
SEL
LVL1
p 53
default
0
0
0
0
0
06h ADC Control
ADCB_HPF
EN
ADCB_HP ADCA_HPF ADCA_HP
FRZ
EN
FRZ
SOFTB
p 54
default
1
0
1
0
0
07h ADC Input
Select
, Invert, Mute
AINB_MUX1
AINB_MUX AINA_MUX1 AINA_MUX0 INV_ADCB
0
p 56
default
0
0
0
0
0
08h DAC Output
Control
HP_GAIN2 HP_GAIN1 HP_GAIN0 DAC_SNG INV_PCMB
VOL
p 57
default
0
1
1
0
0
09h DAC Control DATA_SEL1 DATA_SEL0 FREEZE Reserved DEEMPH
p 58
default
0
0
0
0
0
0Ah ALCA SZC &
PGAA Vol-
ume
ALCA_SR
DIS
ALCA_ZC
DIS
Reserved
PGAA
VOL4
PGAA
VOL3
0
PDN_MICA
1
ADC_I²S/LJ
0
MICBIAS_
LVL0
0
ZCROSSB
0
INV_ADCA
0
INV_PCMA
0
AMUTE
1
PGAA
VOL2
0
PDN_
MICBIAS
1
DIGMIX
0
MICB_
BOOST
0
SOFTA
0
ADCB_
MUTE
0
DACB_
MUTE
0
DAC_SZC1
1
PGAA
VOL1
0
MCLKDIV2
0
MICMIX
0
MICA_
BOOST
0
ZCROSSA
0
ADCA_
MUTE
0
DACA_
MUTE
0
DAC_SZC0
0
PGAA
VOL0
p 59
default
0Bh ALCB SZC &
PGAB Vol-
ume
p 59
default
0Ch ADCA Atten-
uator
p 60
default
0Dh ADCB Atten-
uator
0
ALCB_SR
DIS
0
ADCA_
ATT7
0
ADCB_
ATT7
0
0
ALCB_ZC
DIS
Reserved
0
0
ADCA_
ATT6
0
ADCA_
ATT5
0
ADCB_
ATT6
ADCB_
ATT5
0
PGAB
VOL4
0
ADCA_
ATT4
0
ADCB_
ATT4
0
PGAB
VOL3
0
ADCA_
ATT3
0
ADCB_
ATT3
0
PGAB
VOL2
0
ADCA_
ATT2
0
ADCB_
ATT2
0
PGAB
VOL1
0
ADCA_
ATT1
0
ADCB_
ATT1
0
PGAB
VOL0
0
ADCA_
ATT0
0
ADCB_
ATT0
46
DS679F1