CS42L51_07 Datasheet, PDF (20/88 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 12)
Frequency Response 10 Hz to 20 kHz
Passband
StopBand
StopBand Attenuation (Note 13)
Group Delay
De-emphasis Error
Min
-0.01
to -0.05 dB corner ⁰
to -3 dB corner ⁰
0.5465
50
-
Fs = 32 kHz ^-
Fs = 44.1 kHz ^-
Fs = 48 kHz -
Typ
-
-
-
-
-
10.4/Fs
-
-
-
Max Unit
+0.08
dB
0.4780 Fs
0.4996 Fs
-
Fs
-
dB
-
s
+1.5/+0 dB
+0.05/-0.25 dB
-0.2/-0.4 dB
Notes:
12. Response is clock dependent and will scale with Fs. Note that the response plots (Figure 38 to Figure 41
on page 82) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
13. Measurement Bandwidth is from Stopband to 3 Fs.
SWITCHING SPECIFICATIONS - SERIAL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT C_LOAD = 15 pF.)
RESET pin Low Pulse Width
MCLK Frequency
MCLK Duty Cycle
Slave Mode
Input Sample Rate (LRCK)
Parameters
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
LRCK Edge to SDOUT MSB Output Delay
SDOUT Setup Time Before SCLK Rising Edge
SDOUT Hold Time After SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Symbol
(Note 14)
(Note 15)
Min
1
1.024
45
Quarter-Speed Mode ^F_s
4
Half-Speed Mode F_s
8
Single-Speed Mode ^F_s
4
Double-Speed Mode ^F_s
50
45
1/t_P
-
45
t_s(LK-SK)
40
t_d(MSB)
-
t_s(SDO-SK)
20
t_h(SK-SDO)
30
t_s(SD-SK)
20
t_h
20
Max
-
38.4
55
Units
ms
MHz
%
12.5
kHz
25
kHz
50
kHz
100
kHz
55
%
64•F_s
Hz
55
%
-
ns
52
ns
-
ns
-
ns
-
ns
-
ns
20
DS679F1