CS42L51_07 Datasheet, PDF (27/88 Pages) Cirrus Logic – Low Power, Stereo CODEC with Headphone Amp

CS42L51
4.2 Hardware Mode
A limited feature-set is available when the CODEC powers up in Hardware Mode (see “Recommended Pow-
er-Up Sequence” on page 41) and may be controlled via stand-alone control pins. Table 2 shows a list of
functions/features, the default configuration and the associated stand-alone control available.
Hardware Mode Feature/Function Summary
Feature/Function
Default Configuration Stand-Alone Control
Power Control
CODEC
Powered Up
PGAx
Powered Up
ADCx
DACx
Powered Up
Powered Up
-
MIC Bias
Powered Down
MICx Pre-amplifier
Powered Down
Auto-Detect
Enabled
-
Speed Mode
Serial Port Slave
Serial Port Master
Auto-Detect Speed Mode
Single-Speed Mode
-
MCLK Divide
(Selectable)
“MCLKDIV2” pin 2
Serial Port Master / Slave Selection
(Selectable)
Interface Control
ADC Volume & Gain
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze
ADC
DAC
Digital Boost
Soft Ramp
Zero Cross
Invert
PGAx
Attenuator
ALC
Noise Gate
Line/MIC Input Select
DAC Volume & Gain
HP Gain
AOUTx Volume
Invert
Soft Ramp
Zero Cross
(Selectable)
Disabled
Disabled
Disabled
Disabled
0 dB
0 dB
Disabled
Disabled
Enabled
Continuous DC Subtraction
AIN1A to PGAA
AIN1B to PGAB
G = 0.6047
0 dB
Disabled
Enabled
Disabled
DAC De-Emphasis
(Selectable)
Signal Processing Engine (SPE)
Mix
Beep
Tone Control
Peak Detect and Limiter
Data Selection
Channel Mix
ADC
DAC
Charge Pump Frequency
Disabled
Disabled
Disabled
Disabled
Data Input (PCM) to DAC
ADCA = L; ADCB = R
PCMA = L; PCMB = R
(64xFs)/7
Table 2. Hardware Mode Feature Summary
“M/S” pin 29
“I²S/LJ” pin 3
-
-
-
-
“DEM” pin 4
-
-
-
-
Note
-
-
-
see Section
4.5 on page 38
see Section
4.5 on page 38
see Section
4.6 on page 40
-
-
-
-
see Section
on page 34
-
-
-
-
DS679F1
27