EP7309_05 Datasheet, PDF (43/51 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with Enhanced Digital Audio Interface

JTAG Boundary Scan Signal Ordering
EP7309
High-Performance, Low-Power System on Chip
Table 22. JTAG Boundary Scan Signal Ordering
LQFP TFBGA PBGA
Pin No. Ball
Ball
Signal
Type
1
B3
B1
nCS[5]
O
4
A2
C2
EXPCLK
I/O
5
B1
E4
WORD
O
6
E3
D1
WRITE
O
7
C1
F5
RUN/CLKEN
O
8
C2
D2
EXPRDY
I
9
E2
F4
TXD2
O
10
D2
E1
RXD2
I
13
F3
E2
PB[7]
I/O
14
D1
G5
PB[6]
I/O
15
F2
F1
PB[5]
I/O
16
G3
G4
PB[4]
I/O
17
E1
F2
PB[3]
I/O
18
F1
H7
PB[2]
I/O
19
G2
G1
PB[1]/PRDY2
I/O
20
G1
H6
PB[0]/PRDY1
I/O
23
H3
H1
PA[7]
I/O
24
H1
H5
PA[6]
I/O
25
J3
H2
PA[5]
I/O
26
J2
H4
PA[4]
I/O
27
J1
J1
PA[3]
I/O
28
L3
J4
PA[2]
I/O
29
K2
J2
PA[1]
I/O
30
K1
J5
PA[0]
I/O
31
M3
K1
LEDDRV
O
32
L2
J6
TXD1
O
34
L1
K2
PHDIN
I
35
N3
J7
CTS
I
36
M2
L1
RXD1
I
37
M1
K4
DCD
I
38
P3
L2
DSR
I
39
N1
K5
nTEST1
I
40
N2
M1
nTEST0
I
41
R3
K6
EINT3
I
42
P1
M2
nEINT2
I
43
P2
L4
nEINT1
I
Position
1
3
6
8
10
13
14
16
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
67
69
70
71
72
73
74
75
76
77
78
DS507F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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