EP7309_05 Datasheet, PDF (40/51 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with Enhanced Digital Audio Interface

EP7309
High-Performance, Low-Power System on Chip
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
E1
E2
E3
E4
E5
E6
Name
DD[2]
CL[1]
VDDCORE
D[1]
A[2]
A[4]
A[5]
WAKEUP
VDDIO
nURESET
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
nPOR
nEXTPWR
WRITE
EXPRDY
VSSIO
VDDIO
nCS[2]
nMWE
N/C
CL[2]
VSSRTC
D[4]
nPWRFL
MOSCIN
VDDIO
VSSIO
D[7]
D[8]
RXD[2]
PB[7]
TDI
WORD
VSSIO
nCS[0]
Type
Description
O
LCD serial display data
O
LCD line clock
Core power Digital core power, 2.5V
I/O
Data I/O
O
System byte address
O
System byte address
O
System byte address
I
System wake up input
Pad power Digital I/O power, 3.3V
I
User reset input
Pad power Digital I/O power, 3.3V
I
Expansion clock input
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
Pad ground I/O ground
I
Power-on reset input
I
External power supply sense input
O
Transfer direction
I
Expansion port ready input
Pad ground I/O ground
Pad power Digital I/O power, 3.3V
O
Chip select out
O
ROM, expansion write enable
O
O
LCD pixel clock out
Core ground Real time clock ground
I/O
Data I/O
I
Power fail sense input
I
Main oscillator input
Pad power Digital I/O power, 3.3V
Pad ground I/O ground
I/O
Data I/O
I/O
Data I/O
I
UART 2 receive data input
I
GPIO port B
I
JTAG data input
O
Word access select output
Pad ground I/O ground
O
Chip select out
Table 21. 256-Ball PBGA Ball Listing (Continued)
Ball Location
Name
Type
Description
E7
N/C
O
E8
FRM
O
LCD frame synchronization pulse
E9
A[0]
O
System byte address
E10
D[5]
I/O
Data I/O
E11
VSSOSC
Oscillator
ground
PLL ground
E12
VSSIO
Pad ground I/O ground
E13
nMEDCHG/nBROM
I
Media change interrupt input / internal
rom boot enable
E14
VDDIO
Pad power Digital I/O power, 3.3V
E15
D[9]
I/O
Data I/O
E16
D[10]
I/O
Data I/O
F1
PB[5]
I
GPIO port B
F2
PB[3]
I
GPIO port B
F3
VSSIO
Pad ground I/O ground
F4
TXD[2]
O
UART 2 transmit data output
F5
RUN/CLKEN
O
Run output / clock enable output
F6
VSSIO
Pad ground I/O ground
F7
N/C
O
F8
DD[3]
O
LCD serial display data
F9
A[1]
O
System byte address
F10
D[6]
I/O
Data I/O
F11
VSSRTC
RTC ground Real time clock ground
F12
BATOK
I
Battery ok input
F13
nBATCHG
I
Battery changed sense input
F14
VSSIO
Pad ground I/O ground
F15
D[11]
I/O
Data I/O
F16
VDDIO
Pad power Digital I/O power, 3.3V
G1
PB[1]/PRDY[2]
I
GPIO port B / CL-PS6700 interface
signal
G2
VDDIO
Pad power Digital I/O power, 3.3V
G3
TDO
O
JTAG data out
G4
PB[4]
I
GPIO port B
G5
PB[6]
I
GPIO port B
G6
VSSRTC
Core ground Real time clock ground
G7
VSSRTC
RTC ground Real time clock ground
G8
DD[0]
O
LCD serial display data
G9
D[3]
I/O
Data I/O
G10
VSSRTC
RTC ground Real time clock ground
G11
A[7]
O
System byte address
G12
A[8]
O
System byte address
G13
A[9]
O
System byte address
G14
VSSIO
Pad ground I/O ground
G15
D[12]
I/O
Data I/O
G16
D[13]
I/O
Data I/O
H1
PA[7]
I
GPIO port A
H2
PA[5]
I
GPIO port A
H3
VSSIO
Pad ground I/O ground
H4
PA[4]
I
GPIO port A
H5
PA[6]
I
GPIO port A
40
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