EP7309_05 Datasheet, PDF (16/51 Pages) Cirrus Logic – High-performance, Low-power, System-on-chip with Enhanced Digital Audio Interface

EP7309
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
nCS
A
t_CSd
t_Ad
t_CSh
nMWE
nMOE
HALF-
WORD
WORD
D
EXPRDY
W RITE
t_{H W d}
t_{W D d}
t_MOEd
t_{W Rd}
t_EXs
t_MOEh
t_Ds
t_Dh
t_EXh
Figure 3. Static Memory Single Read Cycle Timing Measurement
Note:
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.
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(All Rights Reserved)
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