CS4245 Datasheet, PDF (42/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
6.4.3 Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels will be muted.
6.4.4 ADC High Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be
frozen and continue to be subtracted from the conversion result. See “High Pass Filter and DC Offset
Calibration” on page 31.
6.4.5 ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit will select master
mode, while clearing this bit will select slave mode.
6.5 MCLK Frequency - Address 05h
7
Reserved
6
MCLK1
Freq2
5
MCLK1
Freq1
4
MCLK1
Freq0
3
Reserved
2
MCLK2
Freq2
1
MCLK2
Freq1
0
MCLK2
Freq0
6.5.1 Master Clock 1 Frequency (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK1 signal. See Table 10 below for the appropriate settings.
Table 10. MCLK1 Frequency
MCLK1 Divider
÷1
÷ 1.5
÷2
÷3
÷4
Reserved
Reserved
MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
x
6.5.2 Master Clock 2 Frequency (Bits 2:0)
Function:
Sets the frequency of the supplied MCLK2 signal. See Table 11 below for the appropriate settings.
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