CS4245 Datasheet, PDF (41/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
Gain
dB
0dB
-10dB
T1=50 µs
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 20. De-Emphasis Curve
6.3.5 DAC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 2. Setting this bit will select master
mode, while clearing this bit will select slave mode.
6.4 ADC Control - Address 04h
7
ADC_FM1
6
ADC_FM0
5
Reserved
4
ADC_DIF
3
Reserved
2
MuteADC
1
HPFFreeze
0
ADC_M/S
6.4.1 ADC Functional Mode (Bits 7:6)
Function:
Selects the required range of output sample rates.
Table 8. Functional Mode Selection
ADC_FM1
0
0
1
1
ADC_FM0
Mode
0
Single-Speed Mode: 4 to 50 kHz sample rates
1
Double-Speed Mode: 50 to 100 kHz sample rates
0
Quad-Speed Mode: 100 to 200 kHz sample rates
1
Reserved
6.4.2 ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Inter-
face Format bit. The options are detailed in Table 9 and may be seen in Figure 7 and 8.
ADC_DIF
0
1
Table 9. ADC Digital Interface Formats
Description
Left Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Format
0
1
Figure
7
8
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