CS4245 Datasheet, PDF (31/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
For each serial port, the serial bit clock must be equal to 128x, 64x, 48x or 32x Fs depending on the desired speed
mode. If operating in asynchronous mode, the serial bit clock SCLK1 must be synchronously derived from MCLK1
and SCLK2 must be synchronously derived from MCLK2. If operating in synchronous mode, SCLK1, and SCLK2
must be synchronously derived from MCLK1. Refer to Table 3 for required serial bit clock to Left/Right clock ratios.
SCLK/LRCK Ratio
Single Speed
32x, 48x, 64x, 128x
Double Speed
32x, 48x, 64x
Quad Speed
32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3 High Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven into the
A/D converter. The CS4245 includes a high pass filter after the decimator to remove any DC offset which could result
in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system.
The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the
HPFFreeze bit (see page 42) is set during normal operation, the current value of the DC offset for the each channel
is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible
to perform a system DC offset calibration by:
1) Running the CS4245 with the high pass filter enabled until the filter settles. See the ADC Digital Filter Charac-
teristics section for filter settling time.
2) Disabling the high pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration
point and the CS4245.
4.4 Analog Input Multiplexer, PGA, and Mic Gain
The CS4245 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA).
The input multiplexer can select one of 6 possible stereo analog input sources and route it to the PGA.
Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing them to be
used for microphone level signals without the need for any external gain. The PGA stage provides ±12 dB of gain
or attenuation in 0.5 dB steps. Figure 14 shows the architecture of the input multiplexer, PGA, and mic gain stages.
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
AIN5A
AIN6A
AIN1B
AIN2B
AIN3B
AIN4B/MICIN2
AIN5B
AIN6B
+32 dB
+32 dB
MUX
PGA
Channel A
PGA Gain Bits
Analog Input
Selection Bits
Channel B
PGA Gain Bits
MUX
PGA
Out to ADC
Channel A
Out to ADC
Channel B
Figure 14. Analog Input Architecture
The “Analog Input Selection (Bits 2:0)” section on page 45 outlines the bit settings necessary to control the input
multiplexer and mic gain. “Channel A PGA Control - Address 07h” on page 43 and “Channel B PGA Control - Ad-
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