CS4245 Datasheet, PDF (34/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTEC pin is an active-
low CMOS driver. See Figure 16 below for a suggested active-low mute circuit.
+V_EE
AOUT
LPF
AC
Couple
560 Ω
Audio
Out
47 kΩ
CS4245
-V_EE
MUTEC
+V_A
MMUN2111LT1
2 kΩ
10 kΩ
-V_EE
Figure 16. Suggested Active-Low Mute Circuit
4.12 Control Port Description and Timing
The control port is used to access the registers, allowing the CS4245 to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to the audio
sample rates. However, to avoid potential interference problems, the control port pins should remain static if no op-
eration is required.
The control port has 2 modes: SPI and I²C, with the CS4245 acting as a slave device. SPI mode is selected if there
is a high to low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C mode is selected by
connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit
address state.
4.12.1 SPI Mode
In SPI mode, CS is the CS4245 chip select signal, CCLK is the control port bit clock (input into the CS4245 from the
microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcon-
troller. Data is clocked in on the rising edge of CCLK and out on the falling edge.
Figure 17 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven
bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which
should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of
the register that is to be updated. The next eight bits are the data which will be placed into the register designated
by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a
47 kΩ resistor, if desired.
There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP
will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is
read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS
high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin
a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK
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