CS4245 Datasheet, PDF (27/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol Min Typ Max
CCLK Clock Frequency
RESET Rising Edge to CS Falling.
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
f_sck
0
-
6.0
t_srs
500
-
ns
t_csh
1.0
-
-
t_css
20
-
-
t_scl
66
-
-
t_sch
66
-
-
t_dsu
40
-
-
(Note 29)
t_dh
15
-
-
t_pd
-
-
50
t_r1
-
-
25
t_f1
-
-
25
(Note 30)
t_r2
-
-
100
(Note 30)
t_f2
-
-
100
Notes: 29. Data must be held for sufficient time to bridge the transition time of CCLK.
30. For f_sck <1 MHz.
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RST
t _srs
CS
t _css
CCLK
t _r2
CDIN
CDOUT
t _scl t _sch
t _f2
t _dsu
t _dh
t _pd
Figure 11. Control Port Timing - SPI Format
t _csh
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