CS4245 Datasheet, PDF (29/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
4. APPLICATIONS
4.1 Recommended Power-Up Sequence
1) Hold RESET low until the power supply, MCLK1, MCLK2 (if used), LRCK1 and LRCK2 are stable. In this state,
the Control Port is reset to its default settings.
2) Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port
will be accessible.
3) The desired register settings can be loaded while the PDN bit remains set.
4) Clear the PDN bit to initiate the power-up sequence.
4.2 System Clocking
The CS4245 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed
modes as shown in Table 1 below.
Mode
Single Speed
Double Speed
Quad Speed
Sampling Frequency
4-50 kHz
50-100 kHz
100-200 kHz
Table 1. Speed Modes
The CS4245 has two serial ports which may be operated synchronously or asynchronously. Serial port 1 consists
of the SCLK1 and LRCK1 signals and clocks the serial audio output, SDOUT. Serial port 2 consists of the SCLK2
and LRCK2 signals and clocks the serial audio input, SDIN.
Each serial port may be independently placed into Single, Double, or Quad Speed mode. The serial ports may also
be independently placed into Master or Slave mode.
4.2.1 Synchronous / Asynchronous Mode
By default, the CS4245 operates in synchronous mode with both serial ports synchronous to MCLK1. In this mode,
the serial ports may operate at different synchronous rates as set by the ADC_FM and DAC_FM bits, and MCLK2
does not need to be provided (the MCLK2 pin may be left unconnected).
If the Asynch bit is set (see “Asynchronous Mode (Bit 0)” on page 43), the CS4245 will operate in asynchronous
mode. The serial ports will operate asynchronously with Serial Port 1 clocked from MCLK1 and Serial Port 2 clocked
from MCLK2. In this mode, the serial ports may operate at different asynchronous rates.
4.2.2 Master Clock
In asynchronous mode MCLK1/LRCK1 and MCLK2/LRCK2 must maintain an integer ratio. In synchronous mode
MCLK1/LRCK1 and MCLK1/LRCK2 must maintain an integer ratio. Some common ratios are shown in Table 2.The
LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of
the device. The ADC_FM and DAC_FM bits and the MCLK Freq bits (see page 42) configure the device to generate
the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard
audio sample rates and the required MCLK and LRCK frequencies.
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