CS4245 Datasheet, PDF (32/54 Pages) Cirrus Logic – 105 dB, 24-Bit, 192 kHz Streo Sudio CODEC

CS4245
dress 08h” on page 44 outlines the register settings necessary to control the PGA. By default, line level input 1 is
selected, and the PGA is set to 0 dB.
4.5 Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals with-
in the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital
passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input
circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient
(such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog
input pairs should be left unconnected.
4.6 Output Connections
The CS4245 DAC’s implement a switched-capacitor filter followed by a continuous time low pass filter. Its response,
combined with that of the digital interpolator, is shown in the “DAC Filter Plots” section beginning on page 50. The
recommended external analog circuitry is shown in the Typical Connection Diagram.
The CS4245 DAC is a linear phase design and does not include phase or amplitude compensation for an external
filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
4.7 Output Transient Control
The CS4245 uses Popguard^™ technology to minimize the effects of output transients during power-up and power-
down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters
when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make
best use of this feature, it is necessary to understand its operation.
4.7.1 Power-up
When the device is initially powered-up, the audio outputs AOUTA and AOUTB are clamped to VQ2 which is initially
low. After the PDN bit is released (set to ‘0’) the DAC outputs begin to ramp with VQ2 towards the nominal quiescent
voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the exter-
nal DC-blocking capacitors to charge to VQ2, effectively blocking the quiescent DC voltage. Audio output will begin
after approximately 2000 sample periods.
4.7.2 Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the
power. In order to do this either the PDN bit should be set or the device should be reset about 250 ms before remov-
ing power. During this time, the voltage on VQ2 and the DAC outputs discharge gradually to GND. If power is re-
moved before this 250 ms time period has passed a transient will occur when the VA supply drops below that of
VQ2. There is no minimum time for a power cycle, power may be re-applied at any time.
4.7.3 Serial Interface Clock Changes
When changing the DAC clock ratio or sample rate it is recommended that zero data (or near zero data) be present
on SDIN for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will
always be in a zero data state. If non-zero serial audio input is present at the time of switching, a slight click or pop
may be heard as the DAC output automatically goes to it’s zero data state.
4.8 Auxiliary Analog Output
The CS4245 includes an auxiliary analog output through the AUXOUT pins. These pins can be configured to output
the analog input to the ADC as selected with the input MUX and gained or attenuated with the PGA, the analog out-
put of the DAC, or alternatively they may be set to high-impedance. See the “Auxiliary Output Source Select (Bits
6:5)” section on page 43 for information on configuring the auxiliary analog output.
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