CS4341_05 Datasheet, PDF (26/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
6.2.2 DIGITAL INTERFACE FORMAT (DIF) BIT 4-6
Default = 000 - Format 0 (I²S, up to 24-bit data, 64 x Fs Internal SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 17 through 19.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DESCRIPTION
I²S, up to 24-bit data, 64Fs Internal SCLK
I²S, up to 16-bit data, 32Fs Internal SCLK
Left Justified, up to 24-bit data,
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 16-bit data
Right Justified, 18-bit data
Identical to Format 1
Table 5. Digital Interface Format
Format
0
1
2
3
4
5
6
1
FIGURE
17
17
18
19
19
19
19
17
6.2.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 20, requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates.
NOTE: De-emphasis is only available in Single-Speed Mode.
6.2.4 POPGUARD^® TRANSIENT CONTROL (POR) BIT 1
Default = 1
0 - Disabled
1 - Enabled
Function:
The Popguard^® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to
the quiescent voltage during power-on or power-down. Please refer to section 4.6 for implementation
details.
6.2.5 POWER DOWN (PDN) BIT 0
Default = 1
0 - Disabled
1 - Enabled
Function:
The device will enter a low-power state when this function is enabled. The power-down bit defaults to
‘enabled’ on power-up and must be disabled before normal operation can occur. The contents of the
control registers are retained in this mode.
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