CS4341_05 Datasheet, PDF (11/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Parameters
Symbol
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
Single-Speed Mode Fs
Double-Speed Mode Fs
LRCK Duty Cycle
SCLK Period
(Note 7) t_sclkw
SCLK rising to LRCK edge
t_sclkr
SDATA valid to SCLK rising setup time
t_sdlrs
Min
1.024
45
4
50
-------1---------
SCLK
Typ
-
-
-
-
(Note 6)
-
-
(^{---5---1----21---})^{---F----s- + 10}
-t-^s---^c--^l--^k--^w--
2
-
SCLK rising to SDATA hold time
t_sdh
MCLK / LRCK = 512, 256 or 128
(^{---5---1----21---})^{---F----s- + 15}
-
SCLK rising to SDATA hold time
t_sdh
MCLK / LRCK = 384 or 192
(^{---3---8----41---})^{---F----s- + 15}
-
Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.
7. See section 4.2.1 for derived internal frequencies.
LRCK
SDATA
t _sclkr
t _sdlrs t _sdh
t _sclkw
*INTERNAL SCLK
Figure 12. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4341.
LRCK
Max
51.2
55
50
100
-
-
-
-
-
Units
MHz
%
kHz
kHz
%
s
s
ns
ns
ns
MCLK
1
N
N
2
*INTERNAL SCLK
SDATA
Figure 13. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK
DS298F5
11