CS4341_05 Datasheet, PDF (22/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
SDA
001000 AD0 W
ACK
MAP
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Figure 22. I²C Write
4.9.3a I²C Write
To write to the device, follow the procedure below while adhering to the control port Switching
Specifications in section 6.
1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must
be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0.
The eighth bit of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP.
This byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register point-
ed to by the MAP.
4) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired
registers are written, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to
repeat the procedure detailed from step 1. If no further writes to other registers are desired,
initiate a STOP condition to the bus.
4.9.3b I²C Read
To read from the device, follow the procedure below while adhering to the control port Switching
Specifications. During this operation it is first necessary to write to the device, specifying the ap-
propriate register through the MAP.
1) After writing to the MAP (see section 4.9.3a), initiate a repeated START condition to the I²C
bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must
match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte
is the R/W bit.
2) Signal the end of the address byte by not issuing an acknowledge. The device will then trans-
mit the contents of the register pointed to by the MAP. The MAP will contain the address of the
last register written to the MAP.
3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive reg-
isters. Continue providing a clock but do not issue an ACK on the bytes clocked out of the de-
vice. After all the desired registers are read, initiate a STOP condition to the bus.
4) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary
to repeat the procedure detailed from step 1. If no further reads from other registers are de-
sired, initiate a STOP condition to the bus.
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DS298F5