CS4341_05 Datasheet, PDF (18/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
Input
MCLK/LRCK
Ratio
512, 256, 128
384, 192
512, 256, 128
Digital Interface Format Selection
I²S up to 16 or ^{Left Justified 24 Right Justified Right Justified}
24 Bits
Bits
18, 20 or 24 Bits
16 Bits
(Format 1)
-
-
X
X
X
X
X
(Format 0)
X
X
-
Internal
SCLK/LRCK
Ratio
32
48
64
Table 4. Internal SCLK/LRCK Ratio
4.2.2 External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are de-
tected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal
Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive pe-
riods of LRCK.
4.3 Digital Interface Format
The device will accept audio samples in several digital interface formats. The desired format is selected
via the DIF0, DIF1 and DIF2 bits in the Mode Control register (see section 6.2.2). For an illustration of the
required relationship between LRCK, SCLK and SDATA, see Figures 17 through 19.
LRCK
Left Channel
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 17. CS4341 Formats 0-1 - I²S up to 24-Bit Data
LRCK
SCLK
SDATA
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data
LRCK
SCLK
SDATA LSB
Left Channel
Right Channel
MSB -1 -2 -3 -4 -5
+7 +6 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 -5
Figure 19. CS4341 Formats 3-6 - Right Justified
+7 +6 +5 +4 +3 +2 +1 LSB
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DS298F5