CS4341_05 Datasheet, PDF (12/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C^®)
Parameter
Symbol
Min
I²C Mode
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 8)
t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL
(Note 9)
t_rc
-
Fall Time of SCL
t_fc
-
Rise Time SDA
t_rd
-
Fall Time of SDA
t_fd
-
Setup Time for Stop Condition
t_susp
4.7
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
25
ns
25
ns
1
µs
300
ns
-
µs
Notes: 8. Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
9. See “Rise Time for Control Port Clock” on page 21 for a recommended circuit to meet rise time
specification.
RST
t _irs
Stop
Start
Repeated
Start
SDA
SCL
t _buf
t _hdst
t _high
t _hdst
tf
t _low t _hdd
t _sud
t _sust
tr
Figure 14. Control Port Timing - I²C Mode
Stop
t _susp
12
DS298F5