CS4341_05 Datasheet, PDF (20/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
4.6.2 Power-Down
To prevent transients at power-down, the device must first enter its power-down state by enabling
RST or setting the PDN bit. When this occurs, audio output ceases and the internal output buffers
are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted
which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the
power to the device may be turned off and the system is ready for the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking
capacitors have fully discharged before turning on the power or exiting the power-down state. If
not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the
device must remain in the power-down state is related to the value of the DC-blocking capacitance.
For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately
0.4 seconds.
4.7 Mute Control
The Mute Control pin goes high during power-up initialization, reset, muting (see section 6.2.1 and 6.5.1)
or if the MCLK to LRCK ratio is incorrect. This pin is intended to be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system
designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute
circuit. See the CDB4341 data sheet for a suggested mute circuit.
4.8 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4341 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 16 shows the recommended power
arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground
and analog ground, REF_GND & AGND should be connected to the analog ground plane.
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor
being the closest. To further minimize impedance, these capacitors should be located on the same layer
as the DAC.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be
positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and
should also be located on the same layer as the DAC. The CDB4341 evaluation board demonstrates the
optimum layout and power supply arrangements.
4.9 Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interfer-
ence problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I²C or SPI.
Notes: MCLK must be applied during all I²C communication.
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