CS4341_05 Datasheet, PDF (19/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
4.4 De-Emphasis
The device includes on-chip digital de-emphasis. The Mode Control (address 01h) bits select either the
32, 44.1 or 48 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for F_s equal to 44.1 kHz.
The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs. Please see section 6.2.3 for the desired de-emphasis control.
De-emphasis is only available in Single-Speed Mode.
Gain
dB
0dB
T1=50 µs
-10dB
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 20. De-Emphasis Curve
4.5 Power-Up Sequence
1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default
settings and VQ will remain low.
2) Bring RST high. The device will remain in a low power state with VQ low.
3) Load the desired register settings while keeping the PDN bit set to 1.
4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when
the POR bit is set to 0. If the POR bit is set to 1, see section 4.6 for a complete description of power-
up timing.
4.6 Popguard^® Transient Control
The CS4341 uses Popguard^® technology to minimize the effects of output transients during power-up and
power-down. This technology, when used with external DC-blocking capacitors in series with the audio
outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It
is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside
from choosing the appropriate DC-blocking capacitors.
4.6.1 Power-Up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to
AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to-
ward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V_Q and
audio output begins. This gradual voltage ramping allows time for the external DC-blocking capac-
itors to charge to the quiescent voltage, minimizing the power-up transient.
DS298F5
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