CS4341_05 Datasheet, PDF (10/34 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
Parameters
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Frequency
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Symbol
Single-Speed Mode Fs
Double-Speed Mode Fs
Single-Speed Mode
Double-Speed Mode
t_sclkl
t_sclkh
t_slrd
t_slrs
t_sdlrs
t_sdh
Min
1.024
45
4
50
40
20
20
-
-
20
20
20
20
Max
51.2
55
50
100
60
-
-
128xFs
64xFs
-
-
-
-
Units
MHz
%
kHz
kHz
%
ns
ns
Hz
Hz
ns
ns
ns
ns
LRCK
SCLK
SDATA
t _slrd
t _slrs
t _sclkh
t _sclkl
t _sdlrs
t _sdh
Figure 11. Serial Input Timing (External SCLK)
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DS298F5